High-speed MOSFET, MODFET and HEMT have been proposed in recent years in which an epitaxially grown strained Si layer interposed with an SiGe (silicon-germanium) layer on a Si (silicon) substrate is used for the channel region. In this strained Si-FET, tensile strain occurs in the Si layer due to the SiGe having a larger lattice constant than the Si, and as a result, the band structure of the Si changes, degeneration is removed and carrier mobility increases. Thus, as a result of using this strained Si layer as a channel region, speed can be increased to about 1.3 to 8 times faster than ordinary speeds. In addition, since ordinary Si substrates can be used for the substrates and the CZ (Czochralski method) can be used for the process, high-speed CMOS can be realized with a conventional CMOS process.
However, although epitaxial growth of a high-quality SiGe layer on an Si substrate is required for epitaxial growth of the aforementioned strained Si layer that is desired to be used as the channel region of an FET, due to the difference in the lattice constants between Si and SiGe, there were problems with crystallinity due to dislocation and so forth. Consequently, the following types of proposals have been made in the prior art.
Examples of methods that have been proposed include a method that uses a buffer layer in which the composition ratio of Ge in the SiGe is changed at constant, gradual increments, a method that uses a buffer layer in which the composition ratio of Ge (Germanium) is changed in steps, a method that uses a buffer layer in which the Ge composition ratio is changed in the form of a super lattice, and a method that uses a buffer layer in which the Ge composition ratio is changed at a constant increment using an Si off-cut wafer (in, for example, U.S. Pat. No. 5,442,205, U.S. Pat. No. 5,221,413, PCT WO98/00857 and Japanese Unexamined Patent Application, First Publication No. 6-252046).
However, the aforementioned examples of the prior art still had the problems described below.
Namely, the SiGe layer deposited using the aforementioned prior art was in a state such that the penetrating dislocation density and surface roughness did not reach the level desirable for use in device and manufacturing processes.
For example, in the case of using a buffer layer in which the Ge composition ratio is changed incrementally, although penetrating dislocation density can be made to be comparatively low, there is the problem of poor surface roughness. Conversely, in the case of using a buffer layer in which the Ge composition ratio is changed in steps, although surface roughness can be made to be comparatively low, there is the problem of large penetrating dislocation density. In addition, in the case of using an off-cut wafer, although dislocation easily passes through in the lateral direction and not the direction of deposition, it is still not possible to achieve an adequate reduction in dislocation. Surface roughness has also not reached the level required by photolithography processes used for LSI and so forth in recent years.